目次
New Features
Common
Complete Renewal of 3D Functions (Part 2)
- Opacity settings for 3D component shapes (enclosures)
- Cross-section view mode
- Ruler function
- Capture function
- Expanded 3D output formats (PDF, DWG, OBJ, STL, IGES)
- Added support for outputting silkscreen and copper (routes, planes, and lands) in 3D output (supported for STEP, PDF, DWG, OBJ, STL, and IGES)
- When importing an ASCII library, STEP shapes included in the data are now linked automatically
PCB DRC Settings & Transfer from Schematics
- Added the ability to edit and check the Default Environment Settings
- Added PCB settings (Net Class, Differential Pair) to the schematic settings
- PCB settings configured in the schematic can now be transferred when transferring to the PCB (selected in a dialog)
- Setting synchronization between schematics and PCBs
CPM Integration
- Refreshed the status icons for CPM-linked projects, and project status is now updated in real time.
- Added the ability to submit CAD file review requests directly from the Project window menu.
- Improved standalone authentication so that the application can be used without restrictions even in offline environments.
- Added support for batch output across multiple projects at once.
- Added support for opening CSiEDA data directly.
Circuit Designer
- Added support for placing Microsoft Word and Excel data on drawings (OLE object insertion).
- Added the ability to place text on the Memo layer.
- Improved the batch settings interface for “Batch Output (New)” to make configuration easier.
PCB Designer
- Added support for exporting TEX files for integration with S-NAP PCB Suite®.
- Added the ability to configure DRC clearance and thermal settings for individual coppers (dynamic copper only).
- Improved DRC unconnected net error reporting. When non-plated through holes (NTHs) or padless pads triggerunconnected net errors, the reason can now be checked.
- Added ON/OFF controls for same-component checks in “DRC Execution Item Settings” (different-net clearance,same-net clearance, and drill keepout areas).
- *The location of the same-component check setting for “MRC Clearance” has also been changed.
- Added the ability to delete unused differential pairs in bulk from the differential pair settings.
- Adjusted the thermal generation logic to improve thermal creation rates.
*Regenerating thermals may change the shape of existing thermals. - Added support for importing and exporting keepout regions in IDF format (routing keepout, drill keepout, component keepout, and height restriction areas).
- Added support for exporting non-circular drill holes in IDF format (exported as board slots).
- Added the ability to switch the display size of grid dots (Large/Small).
Fixed Issues
Common
- Discontinued the Chip1Stop component integration feature due to service migration.
- Added indicators in various settings dialogs to distinguish unused nets and unused differential pairs.
- Increased the Reference designator increment limit to five digits (99,999).
- Revised project file lifecycle management to reduce drive space usage.
- Fixed an issue where component selection did not work correctly during cross-probing.
- Improved annotation processing so that unintended differences in secret attributes are no longer detected.
- Improved CCM category changes so that unnecessary attributes are removed automatically.
- Improved component updating to preserve component control attributes.
- Expanded the number of supported digits for coordinate values in the 3D alignment feature.
- Fixed an issue where the 3D rendering angle was incorrect for specific components.
- Fixed an issue where STEP file export could fail when certain components were included.
- Fixed an issue where DXF import/export did not function correctly in specific environments.
- Excluded RPT files from print targets in GerberPrint batch output.
- Fixed an issue where automatic backups were not saved to the specified destination.
Circuit Designer
- Improved performance in “Connection Information” when handling large numbers of connection lines.
- Fixed an issue where “DRC: Symbol Edit Confirmation” could be detected incorrectly under specific conditions.
- Fixed an issue where gate numbers were displayed when printing components configured to hide gate numbers.
PCB Designer
- Improved via placement by displaying a list of available vias based on the net class, allowing users to select an appropriate via.
- Improved “Update Footprints” so that component height information is retained.
- Fixed issues related to unconnected inner-layer pads.
- Fixed an issue where net names were not assigned to pads within an area when converting lines to copper.
- Fixed an issue where inner-layer pads on DefaultInner were not printed when printing in panel sheet view mode.
- Improved BD Convert to allow assignment of a BD definition layer to multiple layers during conversion.
- Fixed an issue where BD Convert could fail with certain files.
- Fixed an issue where silk cut processing did not work under specific conditions.
- Fixed various minor issues identified through error reports.
